1. Field of the Invention
The present invention relates generally to digital cross-connect systems of parallel time switch structure, and more specifically to a path monitoring system for the digital cross-connect system.
2. Description of the Related Art
A prior art digital cross-connect system of parallel time switch structure is shown in FIG. 1. In this system, TDM input lines #1-#N are respectively connected to test pattern insertion circuits 10.sub.1 .about.10.sub.N to which test patterns are supplied from a multiple test pattern generator 17 so that a unique test pattern can be inserted into a particular timeslot of each TDM (time division multiplex) frame. Each TDM frame contains N idle timeslots and data timeslots (FIG. 2). Using frame and timeslot pulses from a timing generator 16, multiple test pattern generator 17 inserts a test pattern A into idle time slot #1 of each frame of line input #1 and a test pattern B into idle timeslot #2 of each frame of line input #2. Continuing in this way, a test pattern N is inserted into idle timeslot #N of each frame of input line #N. The outputs of the insertion circuits are connected respectively to identical time switches 11.sub.1 -11.sub.N each comprising dual-port random access memories 20.sub.1 .about.20.sub.N that are connected respectively to the outputs of insertion circuits 10.sub.1 -10.sub.N, so that N copies of the output signal of test pattern insertion circuit 10.sub.i are sequentially stored into respectively corresponding RAM's 20.sub.i of all time switches 11.sub.1 -11.sub.N according to a lower-significant-bit output of an address control memory 14 driven by a timeslot counter 15. Each of the time switches 11 includes a selector 21 that is responsive to a higher-significant-bit output of control memory 14 to select one of the outputs of RAM's 20 and applies it to a corresponding one of test pattern check circuits 12.sub.1 .about.12.sub.N. The contents of address control memory 14 are altered or updated by commands from a network management system 13 according to varying network traffic or cable failures to switch incoming line to an alternate output line. For path monitoring purposes, address control memory 14 successively reads all test patterns A, B. . . N from all RAM's of each time switch 11. Each check circuit 12 determines whether each test pattern matches the original pattern in order to evaluate the quality of each all parallel signal paths of time switch at frame intervals. If a mismatch is detected, network management system 13 is notified of this fact to control the address control memory 14.
Since the prior art path monitoring system involves the use of N idle timeslots for each TDM input signal and N unique test patterns, the number of such timeslots and test patterns undesirably increases as input lines increase.